Hct138 datasheet

Datasheet

Hct138 datasheet

Revision history Document ID Release date 74HC_ hct138 HCT138_ Q100 v. The 74HC138; 74HCT138 is a high- speed Si- gate CMOS device and is pin compatible with Low- power Schottky TTL ( LSTTL). 6 — 28 December 5 of 18 Nexperia 74HC138; 74HCT138 3- to- 8 line decoder/ demultiplexer; inverting 8. 74HCT138 Datasheet PDF. Recommended operating conditions 9. hct138 Static characteristics Table 6. The MC74VHCT138A is an advanced high speed CMOS hct138 3- to- 8 decoder fabricated with silicon gate CMOS technology.

Request NXP Semiconductors 74HCT138N: IC download 74HCT138N pdf datasheet, DIP- 16 online from Elcodis, Multiplexers, view , Logic - Signal Switches, 3- TO- 8 LINE DECODER/ DMUX Decoders specifications. 74HC_ HCT138 All information provided in this document is subject to legal disclaimers. Recommended operating conditions Table 5. 74HC138D - The 74HC138; 74HCT138 decodes three binary weighted address inputs hct138 ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7). General description The 74HC138- Q100; 74HCT138- Q100 hct138 decodes three binary weighted address inputs. 74HC138 datasheet datasheet, data sheet, 74HC138 data sheet, hct138 74HC138 pdf pdf. 74HCT138 hct138 PDF Datasheet Search Results. Every output will be HIGH unless E1 E2 are LOW E3 is HIGH.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The ’ HCT138 devices are designed for high- performance memory- decoding or data- routing applications requiring very short propagation delay times. 2 J 0 8; * + Product data sheet Rev. The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs ( A0 when enabled, A3) , A1 provides 8 mutually exclusive active LOW outputs ( Y0 to Y7). In high- performance hct138 memory systems, these decoders hct138 can. 74HCT138PW - The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( datasheet Y0 to Y7). Posted on September 8,.

Hct138 datasheet. HC138 datasheet datasheet, HC138 data sheet, HC138 pdf, data sheet pdf. The device features three enable inputs ( E1 E2 E3). Philips catalog page 33 datasheets, Datasheet search site for Electronic Components , datasheet search, triacs, Semiconductors, integrated circuits, diodes, datasheet, data sheet semiconductors. • The IC06 74HC/ HCT/ HCU/ HCMOS Logic Package Information • The IC06 74HC/ HCT/ HCU/ HCMOS Logic hct138 Package Outlines 74HC/ HCT138. 74hc( tto- 8 line decoder/ demultiplexer; inverting The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7 ). Nexperia 74HC138; 74HCT138 3- to- 8 line decoder/ demultiplexer; inverting 74HC_ HCT138Product data sheet All information provided in this document is subject to legal disclaimers. HC_ HCT138_ Q100 Product.

Download datasheet for 74 HCT138D- Q100 by NXP Semiconductors N. The ’ HCT138 devices are designed for high- performance memory- decoding or data- routing applications requiring.


Datasheet

Could it be that there is a network computer system failure virus, or connected to the computer and network switching equipment that can not access the cable barrier failure caused it? General description The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0, A1 and A2) to eight mutually exclusive outputs ( Y0 to Y7). 74HC/ HCT138 3- to- 8 Line Decoder/ demultiplexer; Inverting. For a complete data sheet, please also download:. The IC06 74HC/ HCT/ HCU/ HCMOS Logic Family Specifications. The ' HC238, ' HCT138, and ' HCT238 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications.

hct138 datasheet

Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs ( A0, A1 and A2).